TransEDA Announces Emulation Edge Suite for Faster Design Verification At 50 Percent Savings

LOS GATOS, Calif.--(BUSINESS WIRE)--Sept. 30, 2002--TransEDA®, the leader in integrated verification solutions for electronic designs, today announced the new Emulation Edge(TM) verification suite, offering integrated circuit (IC) designers using hardware-assisted verification platforms faster time-to-market at half the price.

The Emulation Edge suite enhances existing emulation environments and verification flows to dramatically speed the functional verification process while enabling more efficient use of valuable emulation resources. The suite offers a configurable HDL checker, coverage analysis for simulators and emulators, and test suite analysis in one bundle with a common interface. At up to 50 percent off the regular list price for the combined set of tools, designers can speed time-to-market while keeping tool costs and vendor count to the absolute minimum.

"The Emulation Edge suite enables chip development teams to get the most out of their valuable emulation resources, while improving time-to-market by providing visibility into the verification process," said Tom Borgstrom, vice president of marketing at TransEDA. "The suite is painless to install, integrate, learn and use so designers can get up and running quickly. Add to this the time saved by working with a single vendor for a variety of verification tools, and designers really get an edge."

Emulation Edge Suite - An Integrated Solution

The Emulation Edge verification suite offers a powerful combination of four best-in-class verification tools that work seamlessly together and are easily integrated into existing RTL design flows:

• VN-Check(TM) Configurable HDL Checker: With built-in rule sets and easily configured rules, VN-Check identifies bugs or non-synthesizable constructs before emulation when it is easiest to fix them.
• VN-Cover(TM) Coverage Analysis: The leading Verilog, VHDL and dual-language coverage solution, VN-Cover enables designers to identify and focus test development effort on the areas of a design that have yet to be fully simulated, slashing the number of simulation iterations required.
• VN-Cover Emulator(TM) Coverage Analysis for Emulators: VN-Cover Emulator enables emulator users to gain visibility into the effectiveness of their emulation runs and make more productive use of this valuable resource. Results are compatible with VN-Cover, enabling simulation and emulation coverage to be combined for an accurate picture of overall verification completeness.
• VN-Optimize(TM) Test Suite Analysis: Working seamlessly with VN-Cover and VN-Cover Emulator coverage results, VN-Optimize analyzes test sets from large regression suites and identifies the smallest set of tests that will meet verification goals, dramatically reducing the time and resource requirements for regression testing.

Verification Navigator(TM)

The tools in the Emulation Edge suite are part of TransEDA's Verification Navigator integrated design verification environment. Verification Navigator provides tools that enable IC designers to manage the verification process and shorten verification time. In addition to VN-Check, VN-Cover, VN-Cover Emulator and VN-Optimize, Verification Navigator includes VN-Control Application Specific Test Automation and VN-Property DX(TM) Dynamic Property Checking.

Verification Navigator supports all leading Verilog, VHDL and dual-language simulators; hardware assisted verification platforms from Axis Systems, Cadence Design Systems and Mentor Graphics; and is available on the Solaris, HPUX, AIX, Linux, Windows NT, and Windows 2000 platforms.

Pricing and Availability

The Emulation Edge verification suite, featuring VN-Check, VN-Cover, VN-Cover Emulator and VN-Optimize, is available now through December 31, 2002. Pricing starts at $50,000 (U.S.) for an annual subscription license, a 50 percent savings off list price for the combined tools. For more information on the Emulation Edge suite, visit www.transeda.com/emulationedge.

About TransEDA

TransEDA PLC (symbol TRA on the London Stock Exchange) develops and markets integrated verification solutions for electronic field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), and system-on-chip (SoC) designs. The company's verification IP library includes models for advanced microprocessors and bus interfaces.

TransEDA's design verification software performs application-specific test automation, configurable HDL checking, functional, finite state machine (FSM) and code coverage analysis, and test suite analysis. TransEDA's tier-1 list of customers includes 18 of the world's top 20 semiconductor vendors.

For more information, visit www.transeda.com or contact TransEDA at 983 University Avenue, Building C, Los Gatos, California 95032 U.S.A., telephone (408) 335-1300, fax (408) 335-1319, email info@transeda.com.

Note: TransEDA is a registered trademark and Verification Navigator, VN-Check, VN-Cover, VN-Cover Emulator, VN-Optimize, VN-Control, VN-Property DX and Emulation Edge are trademarks of TransEDA. All other trademarks are properties of their respective holders.

     TransEDA
     Tom Borgstrom, 408.335.1303
     tom.borgstrom@transeda.com
        or
     Armstrong Kendall, Inc.
     Jen Bernier, 415-824-1026
     jen@akipr.com